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A risc cpu in verilog targeted at the iCEbreaker board

Instruction Set Achitecture: design decisions

The design of the CPU for the Robin SoC is characterized by the following characteristics:

Other design properties

The design uses 32-bit words throughout, except for loading and storing bytes. This also means we have no facilities to manipulate 16-bit words whatsoever.

Also, originally there were no POP and PUSH instructions. This resulted in every stack operation to consist of two instructions: one LOADL or STORL instruction and an instruction to increment or decrement the register that was used as the stack pointer (typically register 14), for example MOVER r14,r14,1 to add 4 to register 14. This resulted in rather low density code when used with our C compiler so dedicated POP and PUSH instructions were implemented.

We did not implement similar call and return instructions however as these are less frequent. A call to a known address can be implemented as

    PUSH   r11          ; make sure we can restore this later
    LOADIL r11,#function
    JAL    r11,r11,r0   ; jump to the address in r11, storing pc in r11
    POP    r11

and a return simply as

    JAL    r0,r11,r0    ; jump to addres in r11, ignoring the link because r0 is always 0

The rather peculiar named SETBRA instructions can be used for two things: to set a register to 1 or 0 depending on a condition being met, or conditionally branch to another location using a 16-bit signed offset. This can even be combined to set a register and branch in one instruction. The Robin CPU provides 3 flags that can be tested: zero and negative, which are both set by ALU operations, and always, which by definition is a flag that is always set. Typically an assembler will provided macros to easily implement just a conditional branch or a set register operation with common names.