Robin

Articles documenting the CPU implementation

• Instruction Set Achitecture: design decisions
• Instruction Set Architecture: fields and special registers
• Instruction Set Architecture: ALU operations
• Fetch-Decode-Exec: fetching the instruction bytes
• Fetch-Decode-Exec: decoding signals
• Fetch-Decode-Exec: execution
• Fetch-Decode-Exec: the beginning of a pipeline
• Fetch-Decode-Exec: why writing is faster than reading
• ALU: Which operations to implement
• ALU: A fully combinatorial implementation
• ALU: the role of DSPs
• ALU: implementing shifts with multiplications
• A divider: the algorithm
• A divider: a multicycle implementation
• Odds and ends: conditional Verilog
• Odds and ends: memory mapped io
• Odds and ends: clock cycles per instruction
• Odds and ends: mysteries
• ALU: counting leading zeros